Conformal, uniform dielectric films have many applications in semiconductor manufacturing. In the fabrication of sub-micron integrated circuits (ICs) several layers of dielectric film are deposited. Four such layers are shallow trench isolation (STI), pre-metal dielectric (PMD), inter-metal dielectric (IMD) and interlayer dielectric (ILD). Other applications of conformal dielectric films may be as sacrificial or permanent spacer layers, sacrificial or permanent storage node separation layers, or as dielectric liners for through-wafer vias. All of these layers require silicon dioxide or other dielectric films that fill features of various sizes and have high conformality and uniform film thicknesses across the substrate.
In particular, it is often necessary in semiconductor processing to fill a high aspect ratio gap with insulating material. As device dimensions shrink and thermal budgets are reduced, void-free filling of high aspect ratio (AR) spaces (AR>3.0:1) becomes increasingly difficult due to limitations of existing deposition processes, such as chemical vapor deposition (CVD).
Additionally, challenges associated with shrinking device footprints, increased interconnections, and higher thermal and power loads have created an opportunity for through-wafer vias. New wafer-level packaging technology has evolved from conventional IC interconnect fabrication to the use of through-wafer vias in three-dimensional (3-D) stacked chip packages. Previously, most stacked devices were interconnected by wire bonding at the periphery of the chips. Now, through-wafer vias serve as an electrical connection between stacked chips, analogous to the role of electrical interconnects within an IC. In most embodiments, deep vias are etched through the Si substrate of each device, lined with an insulating material, coated with a diffusion barrier, and filled with a conducting metal. The vias have diameters of approximately 65 um or less and depths of up to 700 um, resulting in high-aspect ratio features that require a highly conformal dielectric film to form a continuous insulating liner in the via.
Other recent and developing applications for conformal, uniform dielectric films are as sacrificial layers in various steps of IC fabrication. A sacrificial layer may be used as a mask for subsequent etching and/or deposition steps, for which a highly uniform film is required. Sacrificial layers may also serve as structural materials during IC fabrication, to be removed following particular processing steps. These applications may require specific film properties relating to conformality, within-wafer uniformity, wet etch rate, mechanical strength, hardness and dielectric constant.
In some applications, the dielectric deposition must take place on a substrate also comprising temperature-sensitive materials with reduced thermal budgets. In that case, the surface preparation, dielectric deposition, and post-deposition treatments must occur at maximum temperatures that may not exceed approximately 100 degrees Celsius, in some embodiments.
An alternative to CVD is atomic layer deposition (ALD). ALD methods involve cycling of self-limiting adsorption steps of reactant gases and can provide thin, conformal films within high aspect ratio features. The ALD process involves exposing a substrate to alternating doses of, usually two, reactant gases. As an example, if reactants A and B are first and second reactant gases for an ALD process, after A is adsorbed onto the substrate surface to form a saturated layer, B is introduced and reacts only with adsorbed A. In this manner, a very thin and conformal film can be deposited. One drawback, however, to ALD is that the deposition rates are very low. Films produced by an ALD cycle are very thin (i.e., about one monolayer); therefore, numerous ALD cycles must be repeated to adequately fill a gap feature. These processes are unacceptably slow in some applications in the manufacturing environment.
Another more recently developed technique useful in dielectric gap fill and other deposition applications in semiconductor processing is referred to as pulsed deposition layer (PDL) processing, sometimes also referred to as rapid surface-catalyzed vapor deposition (RVD). PDL is similar to ALD in that reactant gases are introduced alternately over the substrate surface, but in PDL the first reactant A acts as a catalyst, promoting the conversion of the second reactant B to a film. In ALD the reaction between A and B is approximately stoichiometric, meaning that a monolayer of A can only react with a similar amount of B before the film-forming reaction is complete. The catalytic nature of A in PDL allows a larger amount of B to be added, resulting in a thicker film. Thus, PDL methods allow for rapid film growth similar to using CVD methods but with the film conformality of ALD methods.
PDL-type processes for forming silicon-based dielectrics can use as reactant A, a metal or metalloid catalyst (e.g., trimethylaluminum (TMA)) or metal and metalloid-free catalysts (e.g., an organic acid such as acetic acid (CH3COOH) or an inorganic acid such as phosphoric acid (H3PO4); and as reactant B, a silicon-containing dielectric precursor. As an example of the use of PDL to deposit silicon dioxide on silicon, the first (catalytic) reagent can be trimethylaluminum (TMA) and the second (silicon-containing) reagent can be tris(tert-pentoxy)silanol (TPOSL). A heated silicon substrate is first exposed to a dose of TMA, which is thought to react with the silicon surface to form a thin layer of surface-bound aluminum complex. Excess TMA is pumped or flushed from the deposition sub-chamber. A large dose of TPOSL is then introduced. The aluminum complex catalyzes the conversion of the silanol to silicon oxide until the silanol is consumed, or the growing film covers or otherwise inactivates the catalytic complex. When excess silanol is used, the film growth is usually self-limiting and a thick and uniform conformal film results.
The most significant difference between dielectric depositions using CVD and PDL or ALD is that in the latter case the catalyst precursors and silicon-containing reactant gas are not present in the reactor at the same time. Instead, they are introduced sequentially, generally with a purging step between to minimize gas-phase reactions and to improve step coverage and uniformity of the film.
In CVD, ALD, or PDL systems, a film is often deposited on the chamber walls in addition to the desired location, on the substrate (e.g., silicon wafer) surface. In ALD and PDL reactors, this unwanted deposition could occur as the precursors adsorb to the walls of the reactor in addition to the substrate surface and subsequently react to form film in later PDL/ALD steps. This film can build up on the chamber walls and can act as a source of chemical contaminants and particulates. It has been well documented for many CVD and ALD/PDL systems that a periodic cleaning of the chamber walls to remove these deposits is beneficial. If these chamber cleans are not performed, the film stresses may be so large that the film delaminates from the chamber wall, leading to particle deposition on the substrate surface. However, these chamber cleans reduce chamber productivity.
To eliminate excess chamber wall deposits, PDL apparatuses have been designed as multi-station deposition reactors. The alternating doses of reactant gases may be delivered at separate stations which are substantially isolated from each other and from the main deposition reactor walls. If the reactant gases are physically, as well as temporally, isolated from each other then they do not contribute to unwanted deposition on chamber surfaces.
Typical CVD and ALD chambers have flow through designs in which process gasses are continuously flowed into and exhausted from the process chamber. In CVD processes the total amount of reaction, and of deposited film, increases with reaction time and reactant dose. Due to the time required for B reactants (i.e., silicon containing precursors) in PDL and RVD processes to react with A reactants, and in some cases due to the high cost of such B reactants, some PDL chambers have been designed to be sealed during deposition. When PDL chambers are sealed, all of the reactants remain in the chamber for the entire duration of the deposition, thus achieving a maximum exposure of the substrate to the reactants. Because no B reactant is exhausted from the process chamber until the reaction is complete, so a smaller dose of the B reactants is required. However, in a sealed deposition chamber, the gas flow dynamics may be non-uniform. It is desirable for points on the substrate surface to be exposed to substantially uniform gas doses, so as to achieve substantially uniform film thickness and conformality, among other properties.
It is therefore desirable to develop a method and apparatus for providing uniform gas-flow dynamics in a partially sealed chamber used for PDL processes.